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Rediflex AB - Malmö - Publicerad: 2018-12-06 00:00:00
ASIC Verification Engineer required with at least 10 years’ experience in ASIC Functional Verification.
Very good knowledge of Verilog, System Verilog and UVM methodology.
Long experience in creating/adapting/maintaining block level and system level test benches using UVM/OVM.
Long experience in creating verification plans, test cases for constrained random testing, coverage matrix, verification reports, usage/creation of UVC’s, usage of reference models
Experience with simulation tools from vendors like Mentor, Cadence, and Synopsis.
Experience in ARM CPU subsystems verification.
Experience is C programming.
Must be fluent in English.
Knowledge and experience in debugging Ethernet, Wi-Fi, Bluetooth domain protocols.
Unix/Linux, shell, Perl scripting experience.